Tunneling Effect In Mosfet

DIBL GIDL BTBT and Tunneling effect in CMOS Devices

One must consider these DIBL, GIDL, BTBT, and Tunneling effects while designing in CMOS because these may cause serious issues on the functionality of the design. Understanding these terms is very important in the VLSI design.

Fowler-Nordheim tunneling at SiO2/4H-SiC interfaces in metal-oxide-semiconductor field effect transistors. In: Applied Physics Letters 105.14 (2014), p.142108. ISSN: 0003-6951. Mainly affected by quantum confinement effects, tunneling current through insulators and source-to-drain tunneling current 1-2. A measurement of quantum tunnel current between source-drain has recently shown that it will become detrimental in bulk MOSFET architecture for channel length around 5nm and at low temperature (≤100K) 1. FN tunneling effect; Direct tunneling effect; From the substrate to the gate there is an electron flow due to tunneling effect as shown in the figure above. The process of carrier tunneling through the gate oxide(SiO2) resulting in the gate leakage current flowing into the gate. As shown in the graph above as the Gate voltage increases the. Semiconductor ﬁeld-effect transistor (MOSFET), the tunnel-ing FET (TFET) has recently attracted much interest due to its low OFF current (I OFF) and the possibility of reaching subthreshold slope (S) below the 2.3 (kT/q) limit of a standard MOSFET.1–13 Tunneling FETs with S lower than 60mV/decade at room temperature have been demonstrated. The Tunnel Field-E ect Transistor Devin Verreck,1,2, a) Anne S. Verhulst,1 and Guido Groeseneken1,2 1)imec, Kapeldreef 75, 3001 Leuven, Belgium 2)Department of Electrical Engineering, KU Leuven, 3001 Leuven, Belgium I. INTRODUCTION The tunnel eld-e ect transistor (TFET) is a semicon-ductor device aimed at low-power logic applications that.

Gate Tunneling Effect In Mosfet

The PN junctions between diffusion-substrate or diffusion-well will form diodes and also well-substrate junction will be another diode. Because of that, only the substrate and well terminals are connected to ground or to the supply voltage in PMOS to ensure these diodes will remain reverse biased but however, these reverse biased diodes will conduct a small amount of current Td and leads to junction leakage.

1. Drain Induced Barrier Lowering (DIBL)

DIBL(Drain Induced Barrier Lowering) in MOSFETs leads to a reduction of the Vth of transistors at high Vds. That is Vth decreases when Vds increases.
Vth = Vt0 - n * Vds
Also, DIBL(Drain Induced Barrier Lowering) increases the subthreshold leakage at higher drain voltage (Vds).

2. Gate Induced Drain Leakage (GIDL)

GIDL(Gate Induced Drain Leakage) occurs where the gate partially overlaps with the drain of the MOSFET. It is more pronounced when VDD or Vds levels are at High potential and Vgs is at low potential. GIDL(Gate Induced Drain Leakage) is directly proportional to the gate-drain overlap area and hence transistor width insignificant when Vgd<=VDD (Gate to drain voltage is less than or equal to supply voltage).
When Vgs < 0, this thins out the depletion region between the PN-junction. Since the substrate is at low potential the minority charge carriers that are formed underneath the Gate scatter laterally.

3. Band to Band Tunneling (BTBT)

BTBT(Band to Band Tunneling) occurs across the junction between the source to the body or drain to the body of the transistor when the junction is reverse biased. It also describes the carrier generation in the high field region without any influence of local traps. BTBT (Band to Band Tunneling) is the function of Reverse bias and Doping levels Usually, high halo doping is used to increase the Vth(Threshold Voltage) in order to reduce the Subthreshold leakage, Instead, it causes the BTBT to grow.

The leakage caused by Trap Assisted Tunneling (TAT) when a defect in the Silicon Lattice called traps which reduces the distance that a carrier must travel.

4. Tunneling Effect

There can be two types of tunneling effect

FN tunneling effect
Direct tunneling effect

From the substrate to the gate there is an electron flow due to tunneling effect as shown in the figure above. The process of carrier tunneling through the gate oxide(SiO2) resulting in the gate leakage current flowing into the gate. As shown in the graph above as the Gate voltage increases the tunneling current also increases. The chances of this tunneling effect reduce or drops off exponentially with the oxide thickness (tox). And sometimes the tunneling effect can be purposely be used to form electrically erasable memory devices such as EEPROM.

Tunneling Effect In Mosfet

Tunneling Effect In Mosfet Circuit

If you want to study more about these second-order effects you can refer WESTE 4th edition book and also you can leave a comment in the comment section. Learn and understand all the second-order effects completely if you are a VLSI engineer. These are very important for the interview point also. maintain notes of these and revise before the interview.